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? 1993 data sheet mos integrated circuit m pD4701A incremental encoder counter document no. ic-3303 (1st edition) (o. d. no. ic-6947a) date published march 1997 p printed in japan description the m pD4701A is a counter for an x, y 2-axis incremental encoder. when a two-phase encoder signal is input for the x and y axes, direction discrimination and computation is performed, and count data is output in 8-bit parallel form. in addition, a 3-contact-point input buffer is incorporated, which is useful for applications which use a pointing device such as a mouse or track-ball. the cpu checks the switch input flag or count flag and reads the 12-bit count data in two operations, one for the lower byte and one for the upper byte. the key input flag is output together with the count data in the upper byte. features ? x, y 2-axis incremental encoder counter ? counter input (schmitt-triggered input) x axis: x a , x b 2-phase signal 4-multiplication count method used y axis: y a , y b 2-phase signal ? counters: 12-bit binary up/down counters (2 sets, x & y) reset value: 000h ? count data output: 8-bit parallel latch output 2 (including key input flag) ? on-chip 3-contact-point key input buffer circuit ? cmos ? single +5 v power supply pin configuration (top view) pin names x a , y a : a-phase inputs x b , y b : b-phase inputs right left key inputs middle cs : chip select x/y : x/y counter select u/l : upper/lower byte select d 0 to 7 : data outputs cf : count flag reset x counter sf : count flag reset y reset inputs y t y t y t 1 2 3 4 5 6 7 8 9 10 11 12 x a x b reset x y a y b reset y right left middle sf cf v ss 24 23 22 21 20 19 18 17 16 15 14 13 v dd d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 cs x/y u/l www..net
m pD4701A 2 ordering information part number package m pD4701Ac 24-pin plastic dip (600 mil) m pD4701Agt 24-pin plastic sop (375 mil) block diagram x a x b y a y b reset x reset y right left middle phase determination and edge detection phase determination and edge detection button input circuit x-axis up/down counter data multiplexer & latch y-axis up/down counter count flag circuit switch flag circuit cs x/y u/l cf sf d 0-7 data multiplexer/latch block x-axis counter y-axis counter button input 8 4 8 8 data multiplexer 3-state buffer oe 12-bit latch stb 12-bit latch stb 4-bit latch stb x/y u/l cs d 0 - 7 to count flag circuit
m pD4701A 3 pin functions pin name input/output function cs input chip select input. l input activates outputs d0 to 7. h input sets outputs d0 to 7 to high impedance. output data is latched on the fall edge of cs. l must be maintained during a count data read. x/y input counter select input. l input selects the x counter, and h input selects the y counter. u/l input byte select input. l input selects the lower byte and h input selects the upper byte, controlling data output. reset x input counter reset inputs. reset x input resets the x counter, and reset y input reset y resets the y counter. both are active-h. d 0 to 7 output bus for data output to the cpu. outputs the byte data selected by the x/y and (3-state) u/l inputs. the data latched on the fall of cs is output. cf output counter flag output. set (= l output) when the x or y counter changes while cs = h. reset (= h output) on the fall of cs. while cs = l, count flag output is disabled and the h level is output. sf output switch flag output. becomes active (= l output) when the right, left or middle switch input is l. x a , x b input x counter 2-phase signal input pins (schmitt input) y a , y b input y counter 2-phase signal input pins (schmitt input) right input key switch input pins. key switch input are read as the high-order 4 bits of the left (schmitt input) x counter and y counter upper byte as the internal status. middle v dd +5 v power supply connection pin v ss ground pin cpu interface block mouse interface block power supply block sf key input status upper byte count data lrmc 11 c 10 c 9 c 8 ? ? y ? ? t ? ? y ? ? t
m pD4701A 4 description of operations 1. count operation the m pD4701A executes an up-count and down-count by means of a & b 2-phase signals in the 12-bit up-down counter. an up-count is performed when the a-phase signals (x a , y a ) are phase-advanced, and a down-count is performed when the b-phase signals (x b , y b ) are phase-advanced. the edge of each signal is a count source. (4- multiplication count method: see fig. 1.) fig. 1 count operation timing chart (x, y) a input count operation (x, y) b input forward (up-count) reverse (down-count) 1 2 3 4 5 4 3 2 1 0 this count operation is executed independently for the x axis (x a , x b ) and y axis (y a , y b ). this operation is initialized by reset input (reset x, reset y) only. in an up-count, the next value after fffh is 000h, and in a down-count, the next value after 000h is fffh. 2. operation of count flag, cf the count flag, cf, indicates that a count source (either x a, b or y a, b edge input) has occurred while the cs signal is h, and is an active-low output. cf is reset ( ? h) by cs signal l input. while cs = l, count flag output is disabled and the h level is output. fig. 2 count flag output timing chart x a, b y a, b cf cs count flag output disabled in these periods
m pD4701A 5 3. switch input operation the m pD4701A can process up to 3 contact points as switch inputs (active-l input). switch input is read as part of the count data upper byte together with the switch flag status as an internal status (see fig. 3). these are all active- h outputs. the switch flag status, sf, is equivalent to the switch flag output, sf, described below. fig. 3 data output format 7 sf 6 l 5 r 4 m 3 c 11 2 c 10 1 c 9 0 c 8 7 c 7 6 c 6 5 c 5 4 c 4 3 c 3 2 c 2 1 c 1 0 c 0 bit no. upper byte bit no. lower byte sf : switch flag l : left switch r : right switch m : middle switch c 11 - 0 : count data (12 bit ) 4. operation of switch flag, sf the switch flag, sf, becomes active (active-l output) when the right, left or middle switch input is l. sf can also be read as the switch flag status together with the count data. 5. data read operation the cpu reads the count data and switch input status by controlling cs, x/y and u/l. the relation between these is shown in table 1. (at this time, the data latched on the falling edge of cs is output. if x/y or u/l is switched while cs is still l, the data at the point at which cs changes from h to l is read. when cs is set to h, new data is read into the latch, and the new data is confirmed on the next fall of cs. table 1 data output table cs x/y u/l d 7 d 6 d 5 d 4 d 3 d 2 d 1 d 0 000 x c 7x c 6x c 5x c 4x c 3x c 2x c 1x c 0 001sflrm x c 11 x c 10 x c 9x c 8 010 y c 7y c 6y c 5y c 4y c 3y c 2y c 1y c 0 011sflrm y c 11 y c 10 y c 9y c 8 1 floating
m pD4701A 6 6. connection to cpu system an example of connection to a cpu system is shown in fig. 4. fig. 4 example of connection to cpu system output port a 1 a 0 db 0 - 7 int flag a 2 - a n and iord or mrd y t cpu system cs x/y u/l sf right middle left cf d 0 - 7 x a x b y a y b mouse i/f pD4701A m reset mouse x y m pD4701A pin name description x/y connected to address line a 1 . u/l connected to address line a 0 . cs connects address lines a 2 to a n and the signal resulting from decoding iord in the i/o address mode or mrd in the memory address mode, or an output port. the low level must be maintained during a count data read. d 0 to 7 connected to the data bus. sf, cf when these are used as interrupt signals, they are connected to the cpu int pin. reset x these are connected to a cpu output port or reset signal. reset y the above connections enable the cpu to read the x counter, y counter and switch input status. y t the application circuits and their parameters are for reference only and are not intended for use in actual design-ins.
m pD4701A 7 an example of a m pD4701A data read is shown in fig. 5. fig. 5 example of m pD4701A data read start count value latch count reset x counter low byte read y counter low byte read x counter high byte & switch status read y counter high byte & switch status read data bus high impedance cs = 0 reset x = 1 reset y = 1 x/y = 0 u/l = 0 end x/y = 0 u/l = 1 x/y = 1 u/l = 0 x/y = 1 u/l = 1 cs = 1 * cs must be kept at 0 during the read.
m pD4701A 8 7. application areas two-phase incremental signals are used for detection and measurement of a vector quantity (a quantity that has direction and magnitude), and are widely employed in measuring instruments such as micrometers and linear scales, control systems for digital servo motors, x-y tables, etc., head position control for printers, magnetic disks, etc., robot arm position control, and so on. the m pD4701A incorporates the direction judgment circuit and count pulse generator required for 2-phase incremental signal processing, up/down counters for counting these pulses, and a data latch to hold the read data, in ic form, enabling an x, y 2-axis incremental signal processing system to be implemented easily. in addition, a 3 switch-input buffer is incorporated, enabling this device to be widely used in man-machine interface and centronics interface application areas. 8. operating precautions 1) as the m pD4701A incorporates two sets of 12-bit counters, large transient currents flow during a count operation. adecoupling capacitor of around 0.1 m f should therefore be inserted between v dd and v ss of the m pD4701A. + 5 v v dd v ss m pD4701A tantalum electrolytic, laminated ceramic, or similar capacitor of around 0.1 f (should be mounted right next to the ic.) m 2) if a pulse shorter than the signal phase difference time t sab (350 ns) is input to the a/b phase inputs (x a , x b , y a , y b ) this will result in a miscount. therefore, if pulses shorter than t sab are to be input because of encoder bounds, etc., a filter should be attached to the a/b phase inputs. a or b phase b or a phase pw if pw 3 t sab (350 ns), the count value remains the same before and after pulse input. (up count ? down count or down count ? up count is implemented, and therefore the result is equivalent to no change in the count value.
m pD4701A 9 absolute maximum ratings (t a = 25 c, v ss = 0 v) parameter symbol rating unit supply voltage v dd C0.5 to +7.0 v input voltage v i C1.0 to v dd + 1.0 v output voltage v o C0.5 to v dd + 0.5 v operating temperature t opt C40 to +85 c storage temperature t stg C65 to +150 c permissible loss p d 500 mw dc characteristics (t a = C40 to +85 c, v dd = +5 v 10 %) parameter symbol rating unit test conditions min. max. input voltage high v il 0.8 v input voltage low v ih 2.6 v x a , x b , y a , y b and left, right, middle v ih 2.2 v other than the above output voltage low v ol 0.45 v i ol = 12 ma output voltage high v oh v dd C 0.8 v i oh = C4 ma static consumption current i dd 50 m av i = v dd , v ss input current i i C1.0 1.0 m av i = v dd , v ss 3-state output leak current i off C10 10 m a dynamic consumption current i dd dyn 2maf in = 500 khz hysteresis voltage v h 0.25 v x a , x b , y a , y b and left, right, middle
m pD4701A 10 ac characteristics (t a = C40 to +85 c, v dd = +5 v 10 %) parameter symbol rating unit test conditions min. max. x a , x b input cycle t cyab 2 m sf in = 500 khz y a , y b high-level pulse width t pwabh 900 ns low-level pulse width t pwabl 900 ns signal phase difference time t sab 350 ns r, l high-level pulse width t pwswh 30 m s switch off m low-level pulse width t pwswl 30 m s switch on sf setting delay time t dsfl 50 ns switch on reset delay time t dsfh 50 ns switch off reset pulse width t pwrs 100 ns w, y count enable time t scten 0 ns from reset x , y count clear time t dctcl 100 ns from reset x , y - cf flag setting time t dabcf 120 ns from x a , b , y a , b flag reset time t dcscf 100 ns from cs count setting time t sct 0 ns from cf cs cf enable time t scscf 140 ns from cf cf disable time t habcs 140 ns from x a , b , y a , b pulse width t pwcs 200 ns x/y address setup time t sacs 0 ns to cs u/l address hold time t hcsab 0 ns from cs - d 0 to 7 output delay time t dcsd 150 ns from cs output delay time t dad 100 ns from x/y, u/l floating time t fcsd 50 ns from cs - ac test input waveform 2.6 v 0.45 v 1.5 v 1.5 v test point ac test : the input is driven by 2.6 v for logic 1, and 0.45 v for logic 0. timing measurement is performed at 1.5 v for both logic 1 and logic 0.
m pD4701A 11 fig. 6 two-phase signal & switch signal input timing t cyab t pwabh t pwswl t pwswh t sab t sab t sab t sab t pwabl x a , y a x b , y b right left middle ? ? ? y ? ? ? ? t fig. 7 count flag output timing t pwrs t scten t dabcf t dctcl t scscf t sct t pwcs t habcs t dcscf t sab ? y ? t reset x, y cf cs x a, b y a, b
m pD4701A 12 fig. 8 data output timing t sacs t dcsd t dad t fcsd t hcsa cs x/y u/l d 0 - 7 fig. 9 switch flag signal output timing right left middle sf t dsfl t dsfh
m pD4701A 13 recommended soldering conditions the following conditions (see table below) must be met when soldering this product. please consult with our sales offices in case other soldering process is used, or in case soldering is done under different conditions. types of surface mount device m pD4701Agt soldering process soldering conditions symbol infrared ray reflow peak packages surface temperature: 235 c or below, ir35-00-2 reflow time: 30 seconds or below (210 c or higher), number of reflow process: 2, exposure limit*: none vps peak packages surface temperature: 215 c or below, vp15-00-2 reflow time: 40 seconds or below (200 c or higher), number of reflow process: 2, exposure limit*: none wave soldering solder temperature: 260 c or below, ws60-00-1 flow time: 10 seconds or below, number of flow process: 1, exposure limit*: none partial heating method terminal temperature: 300 c or below, flow time: 10 seconds or below, exposure limit*: none * exposure limit before soldering after dry-pack package is opened. storage conditions: 25 c and relative humidity at 65 % or less. note do not apply more than a single process at once, except for partial heating method. type of through hole mount device m pD4701Ac soldering process soldering conditions symbol wave soldering solder temperature: 260 c or below, flow time: 10 seconds or below
m pD4701A 14 24pin plastic dip (600 mil) notes 1) each lead centerline is located within 0.25 mm (0.01 inch) of its true position (t.p.) at maximum material condition. item millimeters inches a 33.02 max. 1.300 max. b 2.54 max. 0.100 max. c 2.54 (t.p.) 0.100 (t.p.) d 0.50?.10 0.020 +0.004 ?.005 f 1.2 min. 0.047 min. g 3.5?.3 0.138?.012 j 5.72 max. 0.226 max. k 15.24 (t.p.) 0.600 (t.p.) m 0.25 0.010 +0.004 ?.003 n 0.25 0.01 h 0.51 min. 0.020 min. i 4.31 max. 0.170 max. l 13.2 0.520 +0.10 ?.05 2) item "k" to center of leads when formed parallel. p24c-100-600-1 r 0~15 0~15 24 13 112 n b i m r m c d f h g a j k l
m pD4701A 15 p24gt-50-375b-1 item millimeters inches note each lead centerline is located within 0.12 mm (0.005 inch) of its true position (t.p.) at maximum material condition. 15.71 max. 0.87 max. 1.27 (t.p.) 0.40 0.125 0.075 2.9 max. 2.50 0.2 10.3 0.3 7.2 0.2 1.6 0.2 0.15 0.8 0.2 0.12 0.10 0.619 max. 0.035 max. 0.050 (t.p.) 0.016 0.005 0.003 0.115 max. 0.098 0.406 0.283 0.063 0.008 0.006 0.031 0.005 0.004 +0.009 ?.008 a b c d e f g h i j k l m n +0.10 ?.05 +0.10 ?.05 +0.004 ?.002 +0.009 ?.008 +0.012 ?.013 +0.009 ?.008 +0.004 ?.003 24 pin plastic sop (375 mil) 24 13 1 12 a i m m d c n k detail of lead end e f g b h l j 3? +7? ??
m pD4701A 2 no part of this document may be copied or reproduced in any form or by any means without the prior written consent of nec corporation. nec corporation assumes no responsibility for any errors which may appear in this document. nec corporation does not assume any liability for infringement of patents, copyrights or other intellectual property rights of third parties by or arising from use of a device described herein or any other liability arising from use of such device. no license, either express, implied or otherwise, is granted under any patents, copyrights or other intellectual property rights of nec corporation or others. while nec corporation has been making continuous effort to enhance the reliability of its semiconductor devices, the possibility of defects cannot be eliminated entirely. to minimize risks of damage or injury to persons or property arising from a defect in an nec semiconductor device, customers must incorporate sufficient safety measures in its design, such as redundancy, fire-containment, and anti-failure features. nec devices are classified into the following three quality grades: "standard", "special", and "specific". the specific quality grade applies only to devices developed based on a customer designated "quality assurance program" for a specific application. the recommended applications of a device depend on its quality grade, as indicated below. customers must check the quality grade of each device before using it in a particular application. standard: computers, office equipment, communications equipment, test and measurement equipment, audio and visual equipment, home electronic appliances, machine tools, personal electronic equipment and industrial robots special: transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment and medical equipment (not specifically designed for life support) specific: aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems or medical equipment for life support, etc. the quality grade of nec devices is "standard" unless otherwise specified in nec's data sheets or data books. if customers intend to use nec devices for applications other than those specified for standard quality grade, they should contact an nec sales representative in advance. anti-radioactive design is not implemented in this product. m4 96.5 [memo]

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